Short Bytes: A new 5nm test chip has been developed by IBM and its partners which take the advantages of a new fabrication process. The new chip which has contains around 30 billion transistors is created by stacking silicon nanosheets. It is capable of delivering almost twice battery backup on devices and a significant improvement in performance.
IBM, along with its Research Alliance partners, has developed a new 5nm chip that boosts the performance up to 40% at the same power when compared to the 10nm chips currently available in the market.
However, that isn’t the only thing which sets apart these new chips. This time, IBM didn’t go for FinFET (fin field effect) fabrication but stacked silicon nanosheets as the device structure of the transistor, known as GAA (gate-all-around) transistor. The 5nm nail sized test chip so created packs 30 billion transistors.
The approach they used is called Extreme Ultraviolet (EUV) lithography. Almost two years back, they created a 7nm test node with 20 billion transistors using the same approach.
Other than shrinking devices in size, these chips, which are still far from being commercialized, can help us achieve a better future for IoT devices, accelerating cognitive computing, enhancing cloud-based applications, and may be double the battery output of the mobile devices.
According to IBM, their latest development can open the gates for stacked nanosheet devices with electrical properties higher than the ones based on FinFET. They have successfully demonstrated the feasibility of such devices.
Hopefully, the new research might be able to keep Moore’s law
alive. Even Intel whose co-founder Gordon Moore predicted that the number of transistors would double every year, have found it hard to keep with the law.
“Using EUV lithography, the width of the nanosheets can be adjusted continuously, all within a single manufacturing processor chip design,” reads the announcement post.
“This adjustability permits the fine-tuning of performance and power for specific circuits – something not possible with today’s FinFET transistor architecture production, which is limited by its current-carrying fin height.”
It isn’t the case IBM considers the current FinFET technology as inefficient for the creation of 5nm chips. It can be used but merely reducing the space between the fins won’t increase the current flow and eventually the performance.
More details about the ambitious silicon project were disclosed at the 2017 Symposia on VLSI Technology and Circuits Conference in Kyoto, Japan.
According to GlobalFoundries’ CTO Gary Patton, there are plans for commercializing their 7nm manufacturing process by 2018 while the agenda for the 5nm chips using nanosheets is still unclear. GlobalFoundries, along with Samsung, is part of the Research Alliance and has contributed to this research which was conducted at the SUNY Polytechnic Institute in Albany, New York.
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